This invention relates to an asynchronous transfer mode data communication technology and, more particularly, to an asynchronous transfer mode data transmitting apparatus scheduled in an allowed cell rate and a method used therein.
An asynchronous transfer mode, which is hereinbelow abbreviated as xe2x80x9cATMxe2x80x9d, communication has service classes, one of which is called as xe2x80x9cavailable bit ratexe2x80x9d. When the ATM data communication is controlled under the available bit rate, pieces of input data information are stored in a content addressable memory, and the pieces of data information stored in the content addressable memory are scheduled for data transmission at an optimum transmission rate in the feedback control of congestion status.
It is difficult to apply a hardware and a software designed in the constant bit rate to a data communication in the available bit rate. Japanese Patent Publication of Unexamined Application (laid-open) No. 8-242238 discloses a communication control unit for the ATM data communication, which is applicable to the data communication in the available bit rate. The content addressable memory is incorporated in the prior art communication control unit for scheduling the data transmission. The prior art ATM communication system comprises plural ATM switching units, an ATM server, ATM terminals and an ATM network connected thereto. The prior art communication control unit serves as the ATM server or the ATM terminal.
The ATM communication control unit includes a system bus, which is connected to a system memory for storing transmission data, a host computer and a transmitter-receiver. The transmitter-receiver is connected through a physical device to the ATM network, and is further connected to a control memory. The host computer contains a CPU (Central Processing Unit), and the transmitter-receiver includes a receiving section and a transmitting section both connected through the physical device to the ATM network. The transmitter-receiver further includes a host interface connected to the system bus and a control memory interface connected to the control memory.
FIG. 1 shows a part of the transmitting section of the above-described transmitter-receiver disclosed in the Japanese Patent Publication of Unexamined Application. The prior art transmitting section includes a transmitting controller 40, and the transmission controller 40 is associated with a counter 50 and a content addressable memory section 51. The transmission controller 40 cooperates with the counter 50 and the content addressable memory section 51, and varies the transmission timings depending upon the peak rates of the virtual channels VC. The content addressable memory section 51 includes plural content addressable memory cell arrays 511. When an interrogative data pattern is supplied to the content addressable memory cell arrays 511, the content addressable memory cell arrays 511 compares the interrogative data pattern with stored bit strings to see whether or not any stored bit string is matched with interrogative data pattern. When the content addressable memory cell arrays 511 find a stored bit string matched with the interrogative data pattern, the content addressable memory cell arrays output the address assigned to the memory location where the bit string is stored. The addresses arc corresponding to the virtual channels VC, respectively, and a data code stored in each memory location is representative of a time to transmit the next cell to each virtual channel.
The content addressable memory cell arrays 511 are associated with an address decoder 512, a collation register 513 and a selector 516. The transmission controller 40 and the counter 50 are connected to the selector 516, and the selector 516 selectively connects the transmission controller 40 and the counter 50 to the content addressable memory cell arrays 511 under the control of a mode changer 515. The transmission controller 40 instructs the mode changer 515 how to control the selector 516. The collation register 513 is connected through a priority encoder 514 to the transmission controller 40.
The counter 50 increments the stored value at time intervals each equal to a time period required for transmission of a single cell. The stored value is continuously incremented, and, accordingly, is representative of time.
The transmission controller 40 supplies a mode signal to the mode changer 515, and the mode signal is indicative of the write-in mode or the retrieval mode. The mode signal is assumed to indicate the write-in mode. The mode changer 515 controls the selector 516 in such a manner as to connect the transmission controller 40 to the content addressable memory cell arrays 511, and supplies an address signal representative of the memory location corresponding to one of the virtual channels VC. The transmission controller 40 supplies a data code representative of a time (Tp+Ts) to transmit a cell through the selected virtual channel VC through the selector 516 to the content addressable memory cell arrays 511. Then, the data code is stored in the memory location corresponding to the selected virtual channel VC. In this way, data codes are written into the memory locations corresponding to the virtual channels VC.
The transmission controller 40 checks the content addressable memory cell arrays 511 to see whether or not the ATM communication control unit has to transmit a cell through any channel. The transmission controller 40 supplies the mode signal representative of the retrieval mode to the mode changer 515, and causes the selector 516 to connect the counter 50 to the content addressable memory cell arrays 511. The bit pattern representative of the stored value or the present time is supplied through the selector 516 to the content addressable memory cell arrays 511 as the interrogative data pattern. The content addressable memory cell arrays 511 compares the bit pattern with the data codes respectively stored in the memory locations to see whether or not the time to transmit a cell comes. If a data code or data codes are consistent with the bit pattern, logic xe2x80x9c1xe2x80x9d is written into a memory cell or memory cells of the collation register 513 corresponding to the memory location or the memory locations where the data code or the data codes are stored. If plural data codes are matched with the data pattern, logic xe2x80x9c1xe2x80x9d is written into the corresponding memory cells, and the priority encoder 514 prioritizes the virtual channels VC, and the address corresponding to the highest priority is transferred to the transmission controller 40.
Japanese Patent Publication of Unexamined Application No. 10-56492 discloses another prior art communication controlling apparatus. FIG. 2 shows the prior art communication controlling apparatus disclosed in the Japanese Patent Publication of Unexamined Application. The prior art communication controlling apparatus comprises a data transmission controller 2 connected to a transmission rate controller 23 and a PCI bus 7, a transmitter 5 connected between the transmission data controller 2 and a cable 13 and a system memory 4 connected to the PCI bus 7. The transmission rate controller 23 manages the timings to transmit cells through plural virtual channels VC.
The transmission rate controller 23 includes a content addressable memory array 25. Plural memory locations arc defined in the content addressable memory array 8, and each of the memory locations has an address field 8 and a data field 19. The data field 19 is divided into a data sub-field 21 assigned to a time to transmit a cell and another sub-field 17 assigned to a priority flag. The content addressable memory array 25 is associated with a collation register 27, where results of comparison are stored. A selector 24 is connected between the content addressable memory array 25 and the data transmission controller 2, and selectively transfers the addresses xe2x80x9c0xe2x80x9d to xe2x80x9c15xe2x80x9d from the address fields 8 to the data transmission controller 2 depending upon the results of comparison. A timer 3 and a counter 22 generate an interrogative bit pattern representative of a present time and priority, and are connected to the content addressable memory array 25. A write-in controller 6 is further connected to the content addressable memory array 25, and writes a data code representative of a time to transmit a cell into the data sub-field 21 assigned to an associated virtual channel.
The data transmission controller 2 is assumed to check the content addressable memory array 25 to see whether or not a cell is to be transmitted through any one of the virtual channels VC. The timer 3 and the counter 22 supplies the interrogative bit pattern to the content addressable memory array 25, and the interrogative bit pattern is compared with the bit patterns stored in the data fields 19. The present time is assumed to be xe2x80x9c06xe2x80x9d. The counter 22 changes the priority from xe2x80x9c00xe2x80x9d through xe2x80x9c01xe2x80x9d to xe2x80x9c10xe2x80x9d. The priority xe2x80x9c00xe2x80x9d is higher than the priority xe2x80x9c01xe2x80x9d and the priority xe2x80x9c10xe2x80x9d. Two data fields 19 associated with the addresses xe2x80x9c0xe2x80x9d and xe2x80x9c11xe2x80x9d are consistent with the interrogative bit pattern. However, when the counter 22 outputs the priority xe2x80x9c00xe2x80x9d, the data field 19 assigned to the address xe2x80x9c11xe2x80x9d is consistent with the interrogative bit pattern, and the address xe2x80x9c11xe2x80x9d is firstly transferred to the data transmission controller 2. The data transmission controller 2 determines the virtual memory corresponding to the address xe2x80x9c11xe2x80x9d, and instructs the transmitter 5 to transfer a cell through the virtual channel.
FIG. 3 shows a data transmission through plural virtual channels VC1/VC2. The virtual channel VC1 has the priority higher than that of the virtual channel VC2. The present time runs as xe2x80x9c1xe2x80x9d, xe2x80x9c2xe2x80x9d, . . . . . . xe2x80x9c19xe2x80x9d and xe2x80x9c20xe2x80x9d. When the data transmission is scheduled for both virtual channels VC1/VC2, the timer stops incrementing the value (see xe2x80x9c5xe2x80x9d, xe2x80x9c11xe2x80x9d and xe2x80x9c17xe2x80x9d). The allowed cell rate for the virtual channel VC1 is xc2xd, and the virtual channel VC1 is expected to pass a cell at every other time. On the other hand, the allowed cell rate for the virtual channel VC2 is ⅓, and the virtual channel VC2 is expected to pass a cell at every third time. The cells are scheduled to be transmitted through the virtual channel VC1 at xe2x80x9c1xe2x80x9d, xe2x80x9c3xe2x80x9d, xe2x80x9c5xe2x80x9d, xe2x80x9c7xe2x80x9d, xe2x80x9c9xe2x80x9d, xe2x80x9c11xe2x80x9d, xe2x80x9c13xe2x80x9d, xe2x80x9c15xe2x80x9d, xe2x80x9c17xe2x80x9d and xe2x80x9c19xe2x80x9d, and the cells are scheduled to be transmitted through the virtual channel VC2 at xe2x80x9c2xe2x80x9d, xe2x80x9c5xe2x80x9d, xe2x80x9c8xe2x80x9d, xe2x80x9c11xe2x80x9d, xe2x80x9c14xe2x80x9d, xe2x80x9c17xe2x80x9d and xe2x80x9c20xe2x80x9d. Both virtual channels VC1/VC2 are expected to pass the cells at xe2x80x9c5xe2x80x9d, xe2x80x9c11xe2x80x9d and xe2x80x9c17xe2x80x9d. This results in that the time intervals between the data transmissions are prolonged from xe2x80x9c2xe2x80x9d to xe2x80x9c3xe2x80x9d and from xe2x80x9c3xe2x80x9d to xe2x80x9c4xe2x80x9d. Thus, the virtual channels VC1/VC2 do not pass the cells at the allowed bit rates at all times. If plural cells are scheduled to be concurrently transmitted through a large number of associated virtual channels, several cells are left in the system memory without the transmission through the associated virtual channels given the priority lower than that of the others. When cells overflow, some cells may be discarded without data transmission.
The minimum cell rate MCR for the virtual channel VC2 is assumed to be ⅓ in the data transmission shown in FIG. 3. The time interval is prolonged over the minimum cell rate at time xe2x80x9c5xe2x80x9d, xe2x80x9c11xe2x80x9d and xe2x80x9c17xe2x80x9d.
The above-described problems are encountered in both prior arts disclosed in Japanese Patent Publication of Unexamined Application Nos. 8-242238 and 10-56492. The prior art data transmission controllers hardly manage the data transmission through the virtual channels at the allowed cell rate. Sometimes, the prior art data transmission controllers do not achieve the minimum cell rates for the virtual channels. In the worst case, cells are discarded without data transmission.
It is therefore an important object of the present invention to provide a data transmitting apparatus, which transmits cells through virtual channels in the asynchronous transmission mode without any non-transmitted cell.
It is also an important object of the present invention to provide a method used in the data transmitting apparatus.
In accordance with one aspect of the present invention, there is provided a data transmitting apparatus for transmitting cells through plural virtual channels, the data transmitting apparatus comprises a host controller receiving a request for data transmission and including a memory for storing a first piece of data information representative of an allowed cell rate, a second piece of data information representative of a peak cell rate and a third piece of data information representative of a minimum cell rate for each of the plural virtual channels and an available bit rate scheduler connected to the host controller and including a timer incrementing a present time at intervals each equal to a time period required for transmitting each of the cells, an allowed cell rate scheduler connected to the host controller and the timer and receiving the first piece of data information, the third piece of data information and the present time so as to determine a next transmission time and a time limit for a virtual channel selected from the plural virtual channels, a content addressable memory having plural memory locations respectively storing data transmission times for the plural virtual channels, a retriever connected to the allowed cell rate scheduler, the host controller and the content addressable memory and checking the content addressable memory to see whether or not at least one of the data transmission times is equal to one of the next transmission time and the present time and a write-in controller connected to the retriever and the content addressable memory and writing the next transmission time in one of the memory locations as a data transmission time for the virtual channel when there is not any data transmission time equal to the next transmission time, the write-in controller further writes a time not later than the time limit as a data transmission time when there is a data transmission time equal to the next transmission time, and the host controller outputs the data transmission time equal to the present time so as to transmit a cell through the virtual channel.
In accordance with another aspect of the present invention, there is provided a method for scheduling a data transmission through a virtual channel comprising the steps of a) determining a next transmission time and a time limit for the data transmission on the basis of an allowed cell rate, a minimum cell rate and a present time, b) searching a content addressable memory to see whether any one of data transmission times is equal to the next transmission time and c) writing the next transmission time in the content addressable memory as a data transmission time for the virtual channel when the answer at the step b) is given negative or a time not later than the time limit as a data transmission time when the answer is given affirmative.